The present invention is directed to semiconductor integrated circuit design, and more particularly, to semiconductor integrated circuit design that accounts for aging reliability of devices used in the circuit design.
Semiconductor devices are subject to various phenomena that degrade their performance with use and over time. With the evolution of manufacturing process technology, feature sizes have gotten smaller, currently down to tens of nanometers, which accentuate such degradation. Among such phenomena are hot carrier injection (HCI), negative bias temperature instability (NBTI) and time-dependent dielectric (gate oxide) breakdown (TDDB). The resulting changes in device characteristics change the circuit performance and may cause the circuit to fail. Thus, there is a need for simulation of the effects of the phenomena at the design stage of an integrated circuit (IC) to check and analyze the reliability issues and enable the design to be modified, if necessary.
Very large scale integrated circuits (VLSI) may include several hundreds of millions of semiconductor devices. The design and manufacture of VLSI typically makes use of computer aided design tools and programs that integrate synthesis, placement, and routing algorithms with simulation of performance and behavior of the IC and analysis flows for design closure. A known analog simulator is the ‘Simulation Program with Integrated Circuit Emphasis’ (SPICE) and known digital simulators are based on Verilog and VHDL (Very High Speed IC Hardware Description Language).
Electronic design automation (EDA) tools often use standard cell methodology, in which standard cells of different kinds are compiled in a library. Each standard cell defines a layout and certain characteristics (the schematic view) for a respective logic or storage function (the logical view). The schematic view usually provides a netlist, which is a nodal description of devices (individual transistors or connected groups of transistors or storage devices), of their connections to each other in the cell, and of the pins of the standard cell for connecting the cell to other cells and to the external environment. A simulator may then simulate the electronic behavior of the netlist, including parameters such as power consumption, timing and signal propagation delay, as a function of defined input signals, including the resistance, capacitance and inductance effects of interconnections.
The full IC layout is typically defined by a logic synthesis tool that transforms the register-transfer level (RTL) description of the IC into a floor plan netlist using the technology-dependent netlists in the standard cell library, place and route (PNR) tools that then position and connect instances of standard cells of chosen sizes together with design-specific cells, and RC extraction, which calculates the electrical characteristics of inter-connections. The definition of the resulting IC layout is then verified by validation tools, such as Design Rule Check (DRC), Parasitic EXtraction (PEX) and Layout Vs Schematic (LVS), iterating as necessary with the PNR tool.
A standard cell library is a collection of multiple definitions of the same standard logic functions, such as gates, inverters, flip-flops, latches and buffers, in different cell areas and speeds typically of the same height and various widths. A typical standard-cell library contains two main components: a Library Database often including layout, schematic, symbol, abstract, and other logical or simulation views, and a Timing Abstract providing functional definitions, timing, power, and noise information for each cell. The layout data may be saved in a number of formats such as the Cadence Design Exchange Format (‘.def’) and Library Exchange Format (‘.lef’), in accordance with American Standard Code for Information Interchange (ASCII), and the Synopsys Milky Way format. The timing abstract may be stored in Synopsis Liberty format, for example.
Simulating the behavior of the netlist of a VLSI at the device level involves large amounts of data and processing even for the characteristics of the individual devices when fresh (unused). Calculating the usage and hence the aging of the component devices individually to calculate the resulting performance characteristics of the aged VLSI would compound the volume of data and processing. It has been proposed to simplify the aging calculations by performing the calculations at cell level, from the layout, taking account of HCI effects only, and extrapolating the cell fresh slew rate by a ratio of expected degradation, to obtain the consequences for timing only. However, this proposal of simulation is not sufficiently flexible or accurate, does not take account of other aging phenomena, and does not enable simulation of the consequences at VLSI for other performance characteristics, such as power and thermal effects, which it only analyzes in the fresh condition.